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[SPCA] Add more notes on conditional moves and jumps

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Janis Hutz
2026-01-25 13:41:08 +01:00
parent 0770c76ef3
commit a5f0aa40d2
3 changed files with 4 additions and 0 deletions
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semester3/spca/parts/00_asm/03_operations/02_condition-codes.tex
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@@ -20,6 +20,9 @@ and \texttt{OF} is set as above, where \texttt{t = a - b}.
Another instruction that is used is \texttt{testX src2, src1} (X again a size postfix, easier: \texttt{testX b, a}), and acts like computing \texttt{a \& b} and where \texttt{ZF} is set if \texttt{a \& b == 0} Another instruction that is used is \texttt{testX src2, src1} (X again a size postfix, easier: \texttt{testX b, a}), and acts like computing \texttt{a \& b} and where \texttt{ZF} is set if \texttt{a \& b == 0}
and \texttt{SF} is set if \texttt{a \& b < 0}. and \texttt{SF} is set if \texttt{a \& b < 0}.
\inlineex Assume \texttt{x = src1}, \texttt{y = src2} in \texttt{cmpl y, x}. Then, when you use the condition codes with \texttt{cmovle},
the instruction is executed only if $x \leq y$ (i.e. the operands of the compare instructions in the AT\&T syntax are flipped)
\content{Zeroing register} We can use a move instruction, but that is less efficient than using \texttt{xorl reg, reg}, \content{Zeroing register} We can use a move instruction, but that is less efficient than using \texttt{xorl reg, reg},
where \texttt{reg} is the 32-bit version of the reg we want to zero. This works because on 32-bit operations, where \texttt{reg} is the 32-bit version of the reg we want to zero. This works because on 32-bit operations,
the upper 32 bit of the 64 bit register will be zeroed. the upper 32 bit of the 64 bit register will be zeroed.

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semester3/spca/parts/04_exam.tex Normal file
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@@ -0,0 +1 @@
As of HS2025, the following things can be expected at the exam:

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semester3/spca/spca-summary.pdf
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