[SPCA] ASM ops, basic syntax

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2026-01-10 08:36:28 +01:00
parent 02f6df0138
commit 722759c1e8
6 changed files with 70 additions and 5 deletions

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@@ -38,7 +38,7 @@ So, the register \texttt{\$eax} was now the lower 32 bits of \texttt{\%rax}.
Additionally, the following registers are also available, with \texttt{X} to be substituted with 8 through 15: \texttt{\%rX} and the lower 32 bits \texttt{\%rXd}
\subsubsection{Instructions}
Instructions usually have a 3 letter prefix with a one letter postfix, where the postfix indicates the number of bytes.
Instructions usually have a 3 letter \texttt{mnemonic} with a one letter postfix that indicates the number of bytes.
The following postfixes are available: \texttt{b} (byte, 1 byte), \texttt{w} (word, 2 bytes), \texttt{l} (long word, 4 bytes) and \texttt{q} (quad, 8 bytes).
The following options can be passed for source and destination: Registers,
@@ -51,9 +51,11 @@ The instruction will then read the number of bytes, as specified by the postfix
The full syntax for memory address modes is \texttt{D(Rb, Ri, S)}, where
\begin{itemize}[noitemsep]
\item \texttt{D}: Displacement (constant offset), should be 0, 1, 2 or 4 bytes % TODO: This seems to conflict with examples
\item \texttt{D}: Displacement (constant offset), can be 0, 1, 2 or 4 bytes (not bits, if you are confused as I was)
\item \texttt{Rb}: Base register (to which offsets, etc are added). Can be any of the 16 integer registers
\item \texttt{Ri}: Index register: Any, except for \texttt{\%rsp} (and \texttt{\%rbp} is also rarely used)
\item \texttt{S}: Scale factor (1, 2, 4 or 8, to correct offsets)
\end{itemize}
The computation that then happens is the following: \texttt{Mem[ Reg[Rb] + S * Reg[Ri] + D ]}
The computation that happens is the following: \texttt{Mem[ Reg[Rb] + S * Reg[Ri] + D ]}.
Using the \texttt{lea src, dest} instruction, we can get the address computed into the dest register.
Can be abused for similar arithmetic expressions.