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62 lines
4.2 KiB
TeX
62 lines
4.2 KiB
TeX
\newpage
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\subsection{The syntax}
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There are two common styles: AT\&T syntax (common on UNIX) and Intel syntax (common on Windows)
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The state that is visible to us is:
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\begin{itemize}
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\item PC (Program Counter) that contains the address of the next instruction
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\item Register file that contains the most used program data
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\item Condition codes that store status information about most recent arithmetic operation and are used for conditional branching
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\end{itemize}
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To view what \lC\ code looks like in assembly, we can use \texttt{gcc -O0 -S code.c}, which produces \texttt{code.s} which contains assembly code.
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\subsubsection{Registers}
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\texttt{x86} assembly is a bit particular with register naming (register names all start in \%).
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The initial 16-bit version of \texttt{x86} had the following registers (sub registers are registers that can be used to access the high
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(\texttt{h} suffix) or low (\texttt{l} suffix) half of the register. Only registers ending in \texttt{x} feature these sub registers.
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They, as well as \texttt{\%si} and \texttt{\%di} are general purpose):
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\begin{tables}{lll}{Name & Sub-registers & Description}
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\texttt{\%ax} & \texttt{\%ah}, \texttt{\%al} & accumulate \\
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\texttt{\%cx} & \texttt{\%ch}, \texttt{\%cl} & counter \\
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\texttt{\%dx} & \texttt{\%dh}, \texttt{\%dl} & data \\
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\texttt{\%bx} & \texttt{\%bh}, \texttt{\%bl} & base \\
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\texttt{\%si} & - & Source index \\
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\texttt{\%di} & - & Destination index \\
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\hline
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\texttt{\%sp} & - & Stack pointer \\
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\texttt{\%bp} & - & Base pointer \\
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\texttt{\%ip} & - & Instruction pointer \\
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\texttt{\%sr} & - & Status (flags) \\
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\end{tables}
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When the architecture was extended to 32-bit, all registers previously available were retained and a 32 bit version of each was introduced with the prefix \texttt{e}.
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In other words, any 16 bit code would still work as previously, as e.g. the \texttt{\%ax} register was simply now the lower 16 bits of the \texttt{\%eax} register.
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The same happened again when extending to 64-bit, only this time the \texttt{r} prefix was used.
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So, the register \texttt{\$eax} was now the lower 32 bits of \texttt{\%rax}.
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Additionally, the following registers are also available, with \texttt{X} to be substituted with 8 through 15: \texttt{\%rX} and the lower 32 bits \texttt{\%rXd}
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\subsubsection{Instructions}
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Instructions usually have a 3 letter \texttt{mnemonic} with a one letter postfix that indicates the number of bytes.
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The following postfixes are available: \texttt{b} (byte, 1 byte), \texttt{w} (word, 2 bytes), \texttt{l} (long word, 4 bytes) and \texttt{q} (quad, 8 bytes).
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The following options can be passed for source and destination: Registers,
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\content{Immediates} To use a constant value (aka Immediate) in an instruction, we prefix the number with \texttt{\$} (following number is decimal).
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To use hex, we can use \texttt{\$0x}, etc.
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\content{Memory addresses} To treat a register as a memory address, use parenthesis, e.g. \texttt{(\%rax)} interprets the value of \texttt{\%rax} as a memory address.
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The instruction will then read the number of bytes, as specified by the postfix of the instruction.
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The full syntax for memory address modes is \texttt{D(Rb, Ri, S)}, where
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\begin{itemize}[noitemsep]
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\item \texttt{D}: Displacement (constant offset), can be 0, 1, 2 or 4 bytes (not bits, if you are confused as I was)
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\item \texttt{Rb}: Base register (to which offsets, etc are added). Can be any of the 16 integer registers
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\item \texttt{Ri}: Index register: Any, except for \texttt{\%rsp} (and \texttt{\%rbp} is also rarely used)
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\item \texttt{S}: Scale factor (1, 2, 4 or 8, to correct offsets)
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\end{itemize}
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The computation that happens is the following: \texttt{Mem[ Reg[Rb] + S * Reg[Ri] + D ]}.
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Using the \texttt{lea src, dest} instruction, we can get the address computed into the dest register.
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Can be abused for similar arithmetic expressions.
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