[SPCA] Asm intro

semester3/spca/parts/00_asm/00_intro.tex

@@ -0,0 +1,35 @@
+\fancydef{Architecture} Also known as ISA (Instruction Set Architecture) is ``The parts of a processor design that one needs to understand to write assembly code''.
+It includes for example the definition of instructions (and their options) and what registers are available.
+Notable examples are \texttt{x86}, \texttt{RISC-V} (this one is open-source!), MIPS, ARM, etc
+
+\fancydef{Microarchitecture} The implementation of the ISA. It defines the actual hardware layout and how the individual instructions are actually implemented
+and thus also defines things such as core frequency, cache layout and more.
+
+Thus, the ISA is more or less precisely on the boundary of the software/hardware interface.
+
+\inlinedef Complex Instruction Set (CISC):
+\begin{itemize}[noitemsep]
+    \item Stack oriented instruction set: Uses it to pass arguments, save program counter and features explicit push and pop instructions for the stack.
+    \item Arithmetic instructions can access memory
+    \item Condition codes set side effect of arithmetic and logical instructions.
+    \item Design Philosophy: Add new instructions for typical tasks.
+\end{itemize}
+
+
+\inlinedef Reduced Instruction Set (RISC):
+\begin{itemize}[noitemsep]
+    \item Fewer, simpler instructions, commonly with fixed-size encoding. As a result, we might need more to get a given task done. On the other hand,
+          we can execute them with small and fast hardware
+    \item Register-oriented instruction set with many more registers that are used for arguments, return pointers, temporaries, etc.
+    \item Load-Store architecture, i.e. only load and store instructions can access memory
+    \item Thus: No Condition codes
+\end{itemize}
+
+What to choose? Both have advantages that the other has as disadvantage:
+Compiling for CISC is usually easier and usually results in smaller code size.
+For RISC however, compiler optimization can give a huge performance uplift and it can run fast with even a simple chip design.
+
+Today, the choices are made based on outside constraints usually. For desktops and servers, there is enough compute to make anything run fast.
+For embedded systems though, the reduced complexity of RISC makes more sense, but for how long still?
+
+What matters most today are non-technical factors such as existance of code for one ISA or licensing costs (and of course, Geopolitics)

semester3/spca/parts/00_asm/01_syntax.tex

@@ -0,0 +1,11 @@
+\subsection{The syntax}
+There are two common styles: AT\&T syntax (common on UNIX) and Intel syntax (common on Windows)
+
+The state that is visible to us is:
+\begin{itemize}
+    \item PC (Program Counter) that contains the address of the next instruction
+    \item Register file that contains the most used program data
+    \item Condition codes that store status information about most recent arithmetic operation and are used for conditional branching
+\end{itemize}
+
+To view what \lC\ code looks like in assembly, we can use \texttt{gcc -O0 -S code.c}, which produces \texttt{code.s} which contains assembly code.

semester3/spca/parts/00_asm/02_data-types.tex

@@ -0,0 +1,6 @@
+\subsection{Data types}
+\begin{itemize}
+    \item ``\texttt{Integer}'' data type of 1, 2, 4 or 8 bytes that are data values or addresses (untyped pointers)
+    \item ``\texttt{Floating point}'' data type of 4, 8 or 10 bytes
+    \item No aggregate types (such as arrays, structs, etc)
+\end{itemize}

semester3/spca/parts/00_asm/03_operations.tex

@@ -0,0 +1 @@
+\subsection{Operations}

semester3/spca/parts/01_c/03_memory/01_allocation.tex

@@ -12,7 +12,6 @@ it's just that the \textit{compiler} and not the programmer decides when to allo
 \content{Goals} The allocation should have the highest possible throughput and at the same time the best (i.e. lowest) possible memory utilization.
 This however is usually conflicting, so we have to balance the two.
 
-\numberingOff
 \inlinedef \bi{Aggregate payload} $P_k$: All \texttt{malloc}'d stuff minus all \texttt{free}'d stuff
 
 \inlinedef \bi{Current heap size} $H_k$: Monotonically non-decreasing. Grows when \texttt{sbrk} system call is issued.

semester3/spca/parts/01_c/03_memory/03_pitfalls.tex

@@ -12,4 +12,4 @@ Some of these bugs (especially bad references) can usually be found using a debu
 
 Substitute \texttt{malloc} with a \texttt{malloc} that has extra checking code (like \texttt{UToronto CSRI malloc} to detect memory leaks)
 
-Using \texttt{valgrind} (a memory debugger). Or, simply don't bother with \lC\ and use \texttt{Rust}.
+Another option is using \texttt{valgrind} (a memory debugger). Or, simply don't bother with \lC\ and use \texttt{Rust}.

semester3/spca/spca-summary.tex

@@ -12,6 +12,8 @@
 \newcommand{\warn}[1]{\bg{orange}{#1}}
 \newcommand{\danger}[1]{\shade{red}{#1}}
 
+\setNumberingStyle{0}
+
 \begin{document}
 \startDocument
 \usetcolorboxes
@@ -81,6 +83,10 @@ If there are changes and you'd like to update this summary, please open a pull r
 \newsection
 \section{x86 Assembly}
 \input{parts/00_asm/00_intro.tex}
+\input{parts/00_asm/01_syntax.tex}
+\input{parts/00_asm/02_data-types.tex}
+\input{parts/00_asm/03_operations.tex}
+
 
 % ── Intro to C ──────────────────────────────────────────────────────
 \newsection
@@ -106,6 +112,7 @@ If there are changes and you'd like to update this summary, please open a pull r
 \section{Hardware}
 \input{parts/03_hw/00_intro.tex}
 
+
 Remember: Rust and the like have an \texttt{unsafe} block... \lC's equivalent to this is
 \begin{code}{c}
 int main( int argc, char *argv[] ) {