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[CD] x86 lite summary
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\begin{document}
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\startDocument
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\summaryspacing
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\vspace{1cm}
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\begin{center}
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\section{Introduction}
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This summary is still a very early version and structure and content will still change and errors will be fixed.
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It is also likely that it won't be as extensive and detailed as some of my others due to the more applied nature of the course
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and the fact that a Cheat Sheet can be brought to the exam.
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\newpage
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\input{parts/main.tex}
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\subsection{Introduction}
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x86lite is a subset of the full x86 ISA, with only about 20 instructions and only 64-bit signed integers, nothing else.
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It is further interoperable with x86.
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As a quick reminder, the following registers are relevant for x86lite:
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\begin{multicols}{4}
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\begin{itemize}
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\item \texttt{rax}
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\item \texttt{rbx}
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\item \texttt{rcx}
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\item \texttt{rdx}
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\item \texttt{rsi}
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\item \texttt{rdi}
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\item \texttt{rbp} (Base Pointer)
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\item \texttt{rsp} (Stack Pointer)
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\item \texttt{r08}
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\item \texttt{r09}
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\item \texttt{r10}
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\item \texttt{r11}
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\item \texttt{r12}
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\item \texttt{r13}
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\item \texttt{r14}
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\item \texttt{r16}
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\end{itemize}
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\end{multicols}
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Further, the \texttt{rip} points to the next instruction. Then, the CPU has processor state registers, such as \texttt{OF} (set, if the last instruction caused an overflow),
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\texttt{ZF} (set if last result was zero), etc.
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On x86, the heap grows upwards, the stack grows downwards, where the code and data section that precedes the heap in the address space contains program code, constants and globals.
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\subsection{Instructions \& Syntax}
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x86lite uses the AT\&T syntax, where the source comes \textit{before} the destination, immediates are prefixed with a \texttt{\$} and registers with a \texttt{\%}.
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Each mnemonic has suffixes \texttt{q = quadword} (4 words), \texttt{l = long} (2 words), \texttt{w = word} (16 bits) and \texttt{b = byte} (8 bit),
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for example \texttt{movq \$5, \%rax}. This syntax is prevalent in the UNIX ecosystem {\scriptsize (thus is \textit{objectively} superior\dots)}
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The following operands can be passed to instructions:
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\begin{itemize}
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\item \bi{Immediate} (\texttt{Imm}):
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\item \bi{Label} (\texttt{Lbl}):
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\item \bi{Register} (\texttt{Reg}):
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\item \bi{Machine Address} (\texttt{Ind}): Using the format \texttt{disp(base, index, scale)}, with the address computed as \texttt{disp + base + index * scale},
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with \texttt{base} and \texttt{index} registers (\texttt{index} cannot be the \texttt{rsp} reg) and \texttt{disp} and \texttt{scale} \texttt{int32} immediates,
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where in x86lite \texttt{scale} is by default \texttt{8}
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\end{itemize}
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\subsection{List of instructions}
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A list of instructions is also provided on the Moodle page for the course.
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\subsubsection{Arithmetic Instructions}
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\begin{tables}{lll}{Instruction & Explanation & Example}
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\texttt{negq DEST} & 2's complement negation & \verb|negq %rax| \\
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\texttt{addq SRC, DEST} & $\text{DEST} \gets \text{DEST} + \text{DEST}$ & \verb|addq %rbx, %rax| \\
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\texttt{subq SRC, DEST} & $\text{DEST} \gets \text{DEST} + \text{DEST}$ & \verb|subq $4, %rsp| \\
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\texttt{imulq SRC, DEST} & $\text{DEST} \gets \text{DEST} \times \text{DEST}$ & \verb|imulq $4, %rax| \\
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\end{tables}
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\subsubsection{Logic/Bit Manipulation Instructions}
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\begin{tables}{lll}{Instruction & Explanation & Example}
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\texttt{notq DEST} & bitwise not & \verb|notq %rax| \\
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\texttt{andq SRC, DEST} & $\text{DEST} \gets \text{DEST}\ \&\ \text{DEST}$ & \verb|andq %rbx, %rax| \\
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\texttt{orq SRC, DEST} & $\text{DEST} \gets \text{DEST}\ |\ \text{DEST}$ & \verb|orq $4, %rsp| \\
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\texttt{xorq SRC, DEST} & $\text{DEST} \gets \text{DEST}\ \texttt{xor}\ \text{DEST}$ & \verb|xorq $2, %rax| \\
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\texttt{sarq Amt, DEST} & $\text{DEST} \gets \text{DEST} \gg \text{Amt}$ (Arithmetic right shift) & \verb|sarq $4, %rax| \\
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\texttt{shrq Amt, DEST} & $\text{DEST} \gets \text{DEST} \ggg \text{Amt}$ (Logical right shift) & \verb|shrq $1, %rsp| \\
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\texttt{shlq Amt, DEST} & $\text{DEST} \gets \text{DEST} \lll \text{Amt}$ (Logical left shift) & \verb|shlq %rbx, %rax| \\
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\end{tables}
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\subsubsection{Control Flow, Blocks and Labels}
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As you are probably aware of, x86 assembly organizes code into \textit{labeled blocks}.
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Labels are translated away by the linker and loader and the code begins executing at a designated code label (usually ``main'').
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To call a subroutine at a given label, we can use the \texttt{call LABEL} instruction and we can use the \texttt{ret} instruction to return from the procedure.
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\begin{tables}{lll}{Instruction & Description & Notes}
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\texttt{jmp SRC} & $\texttt{rip} \gets \texttt{SRC}$ & Jump to location in \texttt{SRC} \\
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\texttt{call SRC} & Push \texttt{rip}; $\texttt{rip} \gets \texttt{SRC}$ & Push program counter (\texttt{rip}) onto stack, decrement \texttt{rsp} \\
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\texttt{ret} & Pop into \texttt{rip} & Pop top of stack into \texttt{rip}, increment \texttt{rsp} \\
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\end{tables}
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This means that the \texttt{call} and \texttt{ret} instructions act like some sort of abstraction of \texttt{jmp}.
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\subsubsection{Condition Flags \& Codes, Conditional Instructions}
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The following flags are set as side effects from normal instructions:
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\begin{itemize}
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\item \texttt{OF} \textit{overflow}: is set when the result is too big or small to fit in the 64 bit register
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\item \texttt{SF} \textit{sign}: set to the sign of the result
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\item \texttt{ZF} \textit{zero}: set when the result is 0
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\end{itemize}
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From these flags, we can define \textit{condition codes}:
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\begin{tables}{lll}{Condition Codes & Condition & Description}
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\texttt{e} & \verb|ZF| & Equal / Zero \\
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\texttt{ne} & \verb+~ZF+ & Not Equal / Not Zero \\
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\texttt{g} & \verb+~(SF^OF)&~ZF+ & Greater (signed) \\
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\texttt{ge} & \verb+~(SF^OF)+ & Greater or equal (signed) \\
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\texttt{l} & \verb+SF^OF+ & Less (signed) \\
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\texttt{le} & \verb+(SF^OF)|ZF+ & Less or equal (signed) \\
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\end{tables}
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Instead of manually computing \texttt{SRC1 - SRC2} manually, we can instead use the following instructions to set the condition codes:
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\begin{tables}{ll}{Instruction & Description }
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\texttt{cmpq SRC2, SRC1} & Computes \texttt{SRC1 - SRC2} sets condition flags \\
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\texttt{setb CC, DEST} & \texttt{DEST}'s lower byte $\gets$ if \texttt{CC} then 1 else 0 \\
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\texttt{jCC SRC} & \texttt{rip} $\gets$ if \texttt{CC} then \texttt{SRC} else fall through \\
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\end{tables}
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\subsubsection{Stack Operations \& Memory Model}
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To load a pointer into a register, we can use \texttt{leaq Ind, DEST}, which does $\texttt{DEST} \gets \texttt{addr(Ind)}$.
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As mentioned previously, the x86 stack grows downwards, so the \texttt{pushq SRC} instruction computes $\texttt{rsp} \gets \texttt{rsp} - 8; \texttt{Mem[rsp]} \gets \texttt{SRC}$,
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where \texttt{popq DEST} computes $\texttt{DEST} \gets \texttt{Mem[rsp];} \texttt{rsp} \gets \texttt{rsp} + 8$.
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\subsection{Calling Conventions}
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As covered in SPCA, the stack in \texttt{C} stores local variables and other book-keeping data.
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Global variables are stored in the code and data section at the low end of the address space.
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Further, remember that the \texttt{rbp} (base pointer) register by convention contains the \textit{previous value} of \texttt{rsp}.
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\subsubsection{Callee vs Caller Saved registers}
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By convention, the registers \texttt{rbp, rsp, rbx, r12, r13, r14, r15} are \textit{Callee-Saved}, i.e. it is the duty of the \textit{subroutine} (the callee) to restore them.
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All other registers are \textit{Caller-Saved}, meaning that the callee can freely use them.
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\subsubsection{Arguments}
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Function arguments one through six are stored in \texttt{rdi, rsi, rdx, rcx, r8, r9}, respectively, any extra arguments are to be stored on the stack in right-to-left order,
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meaning that for $n > 6$, the $n$-th argument is at $((n - 7) + 2) * 8 + \texttt{rbp}$.
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The return value is stored in \texttt{rax} and the stack must be 16-byte aligned on a call.
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Further, there is a 128 byte ``red zone'', which is a scratch pad for the callee's data, which is there for optimization.
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\section{OCAML}
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\input{parts/ocaml/main.tex}
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\input{parts/00_ocaml/00_basics.tex}
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\section{x86Lite}
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\input{parts/01_x86-lite/00_intro.tex}
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\input{parts/01_x86-lite/01_instructions.tex}
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\input{parts/01_x86-lite/02_instruction-list.tex}
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\section{LLVM}
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\subsection{The basics}
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\input{parts/ocaml/00_basics.tex}
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