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106 lines
3.5 KiB
TeX
106 lines
3.5 KiB
TeX
\subsection{Caches}
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Processors generally improve quicker than memory speed does. Therefore, optimizing memory is necessary, and this is what Caches do.
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\content{Structure} Caches can be defined using $S, E, B$ s.t. $S \cdot E \cdot B = \text{Cache Size}$.\\
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$S = 2^s$ is the set count, $E = 2^e$ is the lines per set, and $B=2^b$ is the bytecount per cache block.
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\content{Address} Using the above, the address can be separated into fields which dictate the cache location:
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\begin{center}
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Address:
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\begin{tabular}{|c|c|c|}
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\hline
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tag & set index & block offset \\
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\hline
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\end{tabular}
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\end{center}
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Since we have $S=2^s$ sets and $B=2^b$ bytes per block, we need $s$ bits for the set index, $b$ bits for block offset. The remaining part (tag) is stored with the cache block and needs to match for a cache hit.
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\inlinedef \textbf{Direct-mapped} i.e. $E=1$ (1 cache line per set only).
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\inlinedef \textbf{2-way Set-Associative} i.e. $E=2$ (2 cache lines per set).
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\content{Example} The importance of caches can quickly be seen when looking at the memory hierarchy:
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\begin{tabular}{llllll}
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\toprule
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\textbf{Cache type} &
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\textbf{What is cached?} &
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\textbf{Where is it cached?} &
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\textbf{Latency (cycles)} &
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\textbf{Managed by} \\
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\midrule
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Registers &
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4/8-byte words &
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CPU core &
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0 &
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Compiler \\
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TLB &
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Address translations &
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On-chip TLB &
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0 &
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Hardware \\
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L1 cache &
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64-byte blocks &
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On-chip L1 &
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1 &
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Hardware \\
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L2 cache &
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64-byte blocks &
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On-chip L2 &
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10 &
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Hardware \\
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Virtual memory &
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4\,kB page &
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Main memory (RAM) &
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100 &
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Hardware + OS \\
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Buffer cache &
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4\,kB sectors &
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Main memory &
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100 &
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OS \\
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Network buffer cache &
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Parts of files &
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Local disk, SSD &
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1{,}000{,}000 &
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SMB/NFS client \\
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Browser cache &
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Web pages &
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Local disk &
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10{,}000{,}000 &
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Web browser \\
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Web cache &
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Web pages &
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Remote server disks &
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1{,}000{,}000{,}000 &
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Web proxy server \\
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\bottomrule
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\end{tabular}
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\subsubsection{Cache Addressing Schemes}
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The cache can see either the virtual or physical address, and the tag and index do \textit{not} need to both use the physical/virtual address.
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\begin{center}
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\begin{tabular}{c|c|c}
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\hline
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\textbf{Indexing} & \textbf{Tagging} & \textbf{Code} \\
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\hline
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Virtually Indexed & Virtually Tagged & VV \\
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Virtually Indexed & Physically Tagged & VP \\
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Physically Indexed & Virtually Tagged & PV \\
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Physically Indexed & Physically Tagged & PP
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\end{tabular}
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\end{center}
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