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12 lines
768 B
TeX
12 lines
768 B
TeX
\newpage
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\subsubsection{Cache misses}
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\begin{itemize}[noitemsep]
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\item \bi{Compulsory / Cold miss} Occurs on the first access of a block (there can't be any data there yet)
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\item \bi{Conflict miss} The cache may be large enough, but multiple lines may map to the current block,
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e.g. referencing blocks 0, 8, 0, 8, \dots would miss every time if they are both mapped to the same cache line.
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This is the typical behaviour for most caches.
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\item \bi{Capacity miss} The number of active cache blocks is larger than the cache
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\item \bi{Coherency miss} See in section \ref{sec:hw-multicore}.
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They happen if cache lines have to be invalidated due in multiprocessor scenarios to preserve sequential consistency, etc
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\end{itemize}
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