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[SPCA] Design fixes

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Janis Hutz
2026-01-26 19:23:23 +01:00
parent fe9dc3344d
commit 02dca2ea18
4 changed files with 2 additions and 3 deletions
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2
semester3/spca/parts/00_asm/01_syntax/00_intro.tex
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@@ -5,7 +5,7 @@ The most obvious difference between the two is that they invert the order of ope
i.e. where the AT\&T syntax has the destination as the second argument, the Intel syntax puts it first. i.e. where the AT\&T syntax has the destination as the second argument, the Intel syntax puts it first.
The state that is visible to us is: The state that is visible to us is:
\begin{itemize} \begin{itemize}[noitemsep]
\item PC (Program Counter) that contains the address of the next instruction \item PC (Program Counter) that contains the address of the next instruction
\item Register file that contains the most used program data \item Register file that contains the most used program data
\item Condition codes that store status information about most recent arithmetic operation and are used for conditional branching \item Condition codes that store status information about most recent arithmetic operation and are used for conditional branching

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semester3/spca/parts/00_asm/01_syntax/01_registers.tex
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@@ -21,5 +21,4 @@ In other words, any 16 bit code would still work as previously, as e.g. the \tex
The same happened again when extending to 64-bit, only this time the \texttt{r} prefix was used. The same happened again when extending to 64-bit, only this time the \texttt{r} prefix was used.
So, the register \texttt{\$eax} was now the lower 32 bits of \texttt{\%rax}. So, the register \texttt{\$eax} was now the lower 32 bits of \texttt{\%rax}.
Additionally, the following registers are also available, with \texttt{X} to be substituted with 8 through 15: \texttt{\%rX} and the lower 32 bits \texttt{\%rXd} Additionally, the following registers are also available, with \texttt{X} to be substituted with 8 through 15: \texttt{\%rX} and the lower 32 bits \texttt{\%rXd}

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semester3/spca/parts/00_asm/01_syntax/02_instructions.tex
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@@ -5,7 +5,7 @@ The following postfixes are available: \texttt{b} (byte, 1 byte), \texttt{w} (wo
The following options can be passed for source and destination: Registers, The following options can be passed for source and destination: Registers,
\content{Immediates} To use a constant value (aka Immediate) in an instruction, we prefix the number with \texttt{\$} (following number is decimal). \content{Immediates} To use a constant value (aka Immediate) in an instruction, we prefix the number with \texttt{\$} (following number is decimal).
To use hex, we can use \texttt{\$0x}, etc. To use hex, we can use \texttt{\$0x}, for binary, we can use \texttt{\$0b}, etc.
\content{Memory addresses} To treat a register as a memory address, use parenthesis, e.g. \texttt{(\%rax)} interprets the value of \texttt{\%rax} as a memory address. \content{Memory addresses} To treat a register as a memory address, use parenthesis, e.g. \texttt{(\%rax)} interprets the value of \texttt{\%rax} as a memory address.
The instruction will then read the number of bytes, as specified by the postfix of the instruction. The instruction will then read the number of bytes, as specified by the postfix of the instruction.

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semester3/spca/spca-summary.pdf
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